1. Field of the Invention
The present invention relates to a layout of a semiconductor device such as a microprocessor, and more specifically to a floor plan of wirings connecting between output pads or input/output pads and circuits for generating or processing signals to or from these pads.
2. Description of Related Art
Microprocessors of 32-bit machine include hardware (data path) for generating address information of a 32-bit length and processing data of a 32-bit length. This data path is constituted by vertically arranging a plurality of units for generating a 32-bit length address or processing a 32-bit length data. Each of the units is composed by arranging 32 layout cells, called a leaf cell, each corresponding to one bit, in a horizontal direction in the order of the bit number in accordance with a given rule. The units within the data path are interconnected through a plurality of buses having a 32-bit length, for exchange of data. These buses are constituted of signal lines formed of metal wiring conductors. The leaf cells of each unit are designed or laid out to the effect that, when the plurality of units are arranged vertically, the wiring conductors of the buses depict a straight line.
On the other hand, the microprocessors of 32-bit machine include 32 address output cells and 32 data input/output cells. The address output cells are provided for outputting address information of one bit to an external of a microprocessor chip, and each of the address output cells is constituted of a bonding pad, an-output buffer, and a control circuit for the output buffer. Similarly, each of the data input/output cells is constituted of a bonding pad, an input/output buffer, and a control circuit for the input/output buffer.
The 32 address output cells and the 32 data input/output cells are respectively connected to corresponding ones of the plurality of units which constitute the data path, through a bundle of metal wiring conductors. Namely, an external address generation unit, which cooperates with other units for generating an external address information, are connected to the address output cells through 32 metal wiring conductors. A data generating and processing unit for generating an output data and for processing an input data, are connected to the data input/output cells through 32 metal wiring conductors.
Referring to FIG. 1, there is shown a conventional floor plan illustrating an address output arrangement of the 32-bit microprocessor. A microprocessor 300 is fabricated in accordance with a semiconductor manufacturing process in which at least two levels of metal wiring conductors and one level of polysilicon wiring conductor are formed. Here, a lower level of the two-level wiring conductors will be called a "first level metal wiring conductor", and an upper level of wiring conductor will be called a "second level metal conductor".
In FIG. 1, only an external address generation unit 302 and an internal address generation unit 304 are depicted for simplification of the drawings, but it it to be understood that a number of units (not shown) are actually arranged in a vertical direction. These units are interconnected through three groups of internal interconnection buses (not shown) extending in parallel to a vertical side 306 of the microprocessor chip. In the shown example, these internal interconnection buses (not shown) are constituted of the second level metal wiring conductors.
Within the external address generation unit 302, a bus for connecting to address output cells 301 (which are hyphened with suffixes "0" to "31" for mutual distinction of respective bits) is provided in addition to the above mentioned three groups of internal interconnection buses. Namely, 32 address output terminals 325 (which are also hyphened with suffixes "0" to "31" for mutual distinction of respective bits) formed on a lower side of the external address generation unit 302 are respectively connected to the address output cells 301-0 to 301-31 through wiring conductors 305 (which are hyphened with suffixes "0" to "31" for mutual distinction of respective bits).
Furthermore, to the external address generation unit 302 are connected a plurality of control wiring conductors (not shown) for transmitting control signals generated in an external address generation controller 303. These control wiring conductors (not shown) are formed of the first level metal wiring conductors, which extend in parallel to opposite horizontal sides 307 and 308 of the microprocessor chip, so as to traverse over a full length of the external address generation unit 302. Within the external address generation unit 302, there are provided four 32-bit registers, a one-out-of-four selector (four-input selector) having four inputs connected to outputs of the four registers, respectively, for selecting and outputting one of the four inputs, and an address incrementer of a 32-bit width, all of which are not shown. These registers, selector and incrementer are controlled by the control signals generated in the external address generation controller 303.
The external address generation unit 302 is constituted of 32 address generation cells (not shown), each of which is configured to generate one bit of external address, which is outputted through an one-bit address output terminal 325-0 to 325-31 provided for each address generation cell. Each of the address generation cells is constituted of four one-bit registers, a one-out-of-four selector, and one full address (all of which are not shown in FIG. 1). The 32 address generation cells are arranged in such a manner that, when the external address generation unit is arranged together with other units, the wiring conductors of the buses straightly extend in parallel to each other. On the other hand, the external address generation controller 303 generates four groups of strobe signals for the respective registers, four selection signals for the one-out-of-four selector, which are supplied in common to the 32 address generation cells through the above mentioned control wiring conductors (not shown).
Referring to FIG. 2, there is shown a block diagram illustrating the construction of the address generation cell, which is generally designated by Reference Numeral 400. The address generation cell 400 four one-bit registers 401, 402, 403 and 404, a one-bit latch 405, a one-out-of-four one-bit selector 406 and a one-bit full adder 407.
Reference Numerals 408, 409 and 427 designate wiring conductors constituting the three groups of buses for internal wirings within the data path. The wiring conductor 427 is used for interconnection with the internal address generation unit 304. The wiring conductors 408 and 409 are connected to two inputs of the register 404, and the wiring conductor 427 is connected to one input of the latch 405. In the layout, these wiring conductors 408, 409 and 427 pass above the leaf cell of the address generation cell 400, and connected to an internal circuit of the address generation cell 400 through contact holes formed at suitable positions.
Reference Numerals 410 to 424 designate control wiring conductors extending from the external address generation controller 30 shown in FIG. 1. These control wiring conductors 410 to 424 are also connected to the internal circuit of the address generation cell 400 through contact holes formed at suitable positions. The control wiring conductor 410 is used for transmitting a clock applied to the latch 405 as a latch signal, and the control wiring conductors 411 and 412 are used to supply a pair of strobe signals to the register 401. The control wiring conductors 413 and 414 are used to supply a pair of strobe signals to the register 402, and the control wiring conductors 415 and 416 are used to supply a pair of strobe signals to the register 403. The control wiring conductors 417, 418 and 419 are used to supply a pair of strobe signals to the register 404, and the control wiring conductors 420, 421, 422 and 423 are used to supply selection signals to the one-out-of-four selector 406.
For simplification of the drawing, in FIG. 2, only one wiring conductor connected to a gate of an N-channel MOS transistor is depicted as each of the control wiring conductors, but it should be understood that, another one wiring conductor connected to a gate of a P-channel MOS transistor is formed in the actual layout.
The control wiring conductor 424 is provided to give a mask signal against the selector 406. For this purpose, the control wiring conductor 424 is connected to one input of an OR circuit 430, which in turn has its other input connected to an output of the selector 406. An output of the OR circuit 430 is connected to an address output terminal 425 for outputting an output signal from the address generation cell 400 to the address output cell 301. This address output terminal 425 is also connected to an input of the full adder 407.
Reference Numeral 426 shows a signal line for transmitting a carry output of the full adder 407, and Reference Numeral 428 indicates a signal line for transmitting a carry output to be supplied to the full adder 407. Reference Numeral 429 designates a signal line for transmitting an output signal of the full adder 407, and the signal line 429 is connected through an inverter 431 to one input of each of the four registers 401, 402, 403 and 404. An output of the latch 405 is connected through two cascaded inverters 432 and 433 to the other input of each of the registers 401, 402 and 403.
The control wiring conductors 410 to 424 are constituted of the first level conductors which extend in a horizontal direction in FIG. 1 and which are formed in common to the 32 address generation cells within the external address generation unit 302. In the layout, the signal lines 426 and 428 are formed of the first level conductors extending in the horizontal direction in FIG. 1. The wiring conductors 408, 409 and 427 are common to a leaf cell of each bit within the data path, and, are, in the actual layout, formed of the second level metal wiring conductors extending in a vertical direction in FIG. 1. The signal line 429 is used for transmitting an internal signal within the address generation cell 400.
Referring to FIG. 3, there is shown a layout diagram of the second level wiring conductors within the address generation cell. In FIG. 3, a cell 500 corresponds to the address generation cell 400 in FIG. 2. In addition, wiring conductors 508, 509 and 527, an address output terminal 525 and a signal line 529 in FIG. 3 correspond to the wiring conductors 408, 409 and 427, the signal line 429 in FIG. 2, respectively.
Here, a wiring for connecting the address output terminal 525 to the address output cell 301 will be explained. The address output terminal 525 is located at a lower end of the address generation cell 500. A lead-out line cannot be taken out from the address output terminal 525 toward an upper end of the address generation cell 500, since it conflicts the signal line 529 of the second level metal wiring conductor. Accordingly, a lead-out line from the address output terminal 525 is taken out from only the lower end of the address generation cell 500.
As shown in FIG. 1, the 32 address output cells 301-0 to 301-15 are arranged along the side 306 of the microprocessor chip 300. On the other hand, the external address generation unit 302 is located at a position which is different from an end of the data path. Specifically, within the data path, other units exist between the external address generation unit 302 and each of the sides 307 and 308 of the microcomputer chip. The address output terminals 325 of the external address generation unit 302 in FIG. 1 correspond to the address output terminal 525 shown in FIG. 3.
As shown in FIG. 1, the wiring conductors 305-0 to 305-31 between the external address generation unit 302 and the address output cells 301-0 to 301-31 are formed by downward taking out from the 32 address output terminals 325-0 to 325-31 by means of the second level metal wiring conductor, and then changing to the first level metal wiring conductor firstly extending to the side 306 of the microprocessor chip 300 in a horizontal direction and further upward or downward extending in a vertical direction.
In the case that the wiring conductors between the external address generation unit 302 and the address output cells 301 are formed as mentioned above, a wiring area for the 32 first level metal wiring conductors is required between the external address generation unit 302 and the internal address generation unit 304. In addition, as will be understood from FIG. 1, a wiring area for 16 first level metal wiring conductors is required between the external address generation unit 302 and the internal address generation unit 304 and the address output cells 301-0 to 301-31 located along the side 306 of the chip 300. The wiring area of the latter case is a minimum value, but an increase area becomes necessary if a central position of a row of the address output cells (the address output cell 301-15) is deviated or separated from a center of the former wiring area (a center of an area between the external address generation unit 302 and the internal address generation unit 304).
Here, trace the wiring conductor for each bit. For example, the wiring conductor 305-0 connecting between the address output terminal 325-0 to the address output cell 301-0 is formed by the second level metal wiring conductor extending form the output terminal 325-0 formed on the lower side of the external address generation unit 302, in parallel to the side 306 of the chip 300, over a length corresponding to a width of the wiring area for the 32 first level metal wiring conductors. This second level metal wiring conductor is connected to the first level metal wiring conductor, which extends toward the side 306 of the chip 300, in parallel to the side 307 of the chip 300, over a width of the data path to the right side of the data path. At the right side of the data path, the first level metal wiring conductor is bent into a downward direction to extend to a level of the address output cell 301-0, and then, also bent into a horizontal direction so as to extend to the address output cell 301-0, in parallel to the side 307 of the chip 300, over a length corresponding to a width of the wiring area for the 16 first level metal wiring conductors.
On the other hand, the wiring conductor 305-15 connecting between the address output terminal 325-15 to the address output cell 301-15 is formed by the second level metal wiring conductor extending form the output terminal 325-15 formed on the lower side of the external address generation unit 302, in parallel to the side 306 of the chip 300, over a length corresponding to a width of the wiring area for the 16 first level metal wiring conductors. This second level metal wiring conductor is connected to the first level metal wiring conductor, which extends toward the side 306 of the chip 300, in parallel to the side 307 of the chip 300, over a half of the width of the data path. At the fight side of the data path, the first level metal wiring conductor further extends straightly to the address output cell 301-15, in parallel to the side 307 of the chip 300, over a length corresponding to a width of the wiring area for the 16 first level metal wiring conductors.
In the above mentioned conventional example, the total length of the wiring conductor 305-0 reaches about 2.56 times the total length of the wiring conductor 305-15.
In conclusion, since the conventional example is so configured that the wiring conductor taken out from the address generation cell can be extended only a downward direction, the following problems have been encountered:
(1) A wiring area corresponding to the number of the address bits is required in a direction of taking out the wiring conductor from the address generation cell. In other words, a large wiring area is required within the data path zone. PA0 (2) Between the data path zone and the output cell zone (output terminal zone), a wiring area corresponding to at least a half of the number of the address bits is required. In other words, a large wiring area is required at an outside of the data path. PA0 (3) Since a necessary chip area increases by the two wiring areas, a chip cost correspondingly increases. PA0 (4) The wiring conductor 427 extending from the internal address generation unit 304 is inevitably increased by the width of the wiring area mentioned in the above item (1), and therefore, a bus transmission rate of the wiring conductor 427 correspondingly drops. PA0 (5) Since the wiring conductors 305 extending from the address output terminals 325 to the address output cells 301 become long, an address transmission rate of the wiring conductor 305 correspondingly drops. PA0 (6) As mentioned above, since a large difference exists between the longest one and the shortest one of the wiring conductors 305, the address transmission rate through the wiring conductors 305 is different from one bit to another bit, a timing design becomes difficult.
As a result,
In order to compensate the drop of the bus transmission rate, if the size of an output buffer (not shown) within the internal address generation unit 304 has to be made large, the area of the unit 304 becomes large. This increases the chip cost and the consumed electric power.
In order to compensate the drop of the transmission rate, if the size of an output buffer (not shown) within each address generation cell has to be made large, the area of the address generation cell becomes large. This increase the chip cost and the consumed electric power.